姓名:董社勤

职称:副教授

电话:62785564

邮箱:dongsq@tsinghua.edu.cn

教育背景

工学学士 (计算机科学与技术), 哈尔滨工业大学, 中国, 1985;

工学硕士 (半导体物理与器件), 哈尔滨工业大学, 中国, 1988;

工学博士 (机电控制及自动化), 哈尔滨工业大学, 中国, 1996;

博士后, 浙江大学, 中国, 1999.

社会兼职

清华大学计算机科学与技术系: 研究生工作组长 (2000-2003);

清华大学计算机科学与技术系EDA实验室: 实验室主任 (2000-2008);

ACM/IEEE ASP-DAC: 程序委员会委员 (2010-2011);

海淀区科委: 电子信息专家委员会委员 (2003-);

Joint Conference of Information Science: 程序委员会主席、指导委员会委员 (2007-2008);

日本早稻田大学: 访问学者、客员教授 (2007-2009);

香港中文大学: 副研究员 (2003-2005).

研究领域

集成电路物理设计理论与算法,数字系统设计自动化,集成电路芯片设计;现代优化算法及其应用

研究概况

我主要从事集成电路布图理论及算法研究,近年来在这些方面取得一系列研究成果。基于这些工作,我成功地争取到日本北九州政府及日本早稻田大学的支持,设立清华大学计算机系EDA日本北九州研究基地,开展长期的国际合作研究。

针对集成电路布图规划和布局问题,我提出了基于平面T型划分的角模块序列布图表示理论,包括数据结构、包含最优解的布图表示及其理论、无冗余可遍历的解变换三路线模型等,已经成为该领域有重要影响的工作之一。零死区固定边框布图表示及方程求解算法的提出,是一项重要的理论及技术突破。

结合集成电路物理设计中组合优化问题的研究,我提出了既有全局平滑又有局部平滑机制的解空间平滑优化算法。结合集成电路布局问题,我提出了最小自由度优先的布局算法,是迄今为止世界上最快的固定边框布局算法,并已被成功应用在三维装箱、FPGA规划等方面。

在模拟电路物理设计和数模混合SOC电路物理设计方向上,我提出了基于信号流的布图方法以及模拟电路布图约束自动提取算法。我还提出了针对热效应的模拟电路失配模型、数模混合电路布局的快速噪声模型、及考虑热效应的模拟电路布图算法。这些研究成果已转让至日本精工、Jedat等公司,并成功应用在其EDA产品中。

针对具有异构资源的FPGA布图问题、2.5D集成电路布图问题、3D集成电路布图及互连优化问题、热问题、多电压布图问题等研究难点,我提出了一系列相应的优化方法。针对非直角互连的X结构和Y结构的布图问题,我提出了新的布图规划表示模型和精确的互连估计模型。此外,我还提出了指令定制的优化算法以及体系结构探索算法。

研究课题

清华大学与日本早稻田大学合作项目: 系统芯片及其设计自动化研究 (2006-);

清华大学与日本东芝公司合作项目: 模拟电路物理设计研究 (2007-2010);

国家自然科学基金重点项目: 可编程可重构SOC芯片系统结构及关键技术 (2006-2008);

国家自然科学基金项目: 解空间平滑及其在片上系统布图规划和互连资源规划中的应用 (2005-2007);

国家自然科学基金重大研究计划项目: 数模混合片上系统布图规划与布局算法 (2004-2006);

国家自然科学基金与香港研究资助局联合项目: 基于最小自由度优先的优化算法及其应用研究 (2003-2005);

清华大学与日本精工、Jedat合作项目: 模拟电路布图研究 (2002-2005);

国家自然基金国际合作重点项目: 国际SOC 芯片设计中心 (2001-2004).

奖励与荣誉

北京市科学技术二等奖——超深亚微米SOC物理级CAD关键技术及其应用 (2007);

教育部国家自然科学二等奖——超大规模集成电路物理级优化和验证问题基础研究 (2006);

清华大学研究生教育管理“林枫奖”一等奖: (2002).

学术成果

[1] Xu He, Sheqin Dong, Yuchun Ma, Signal Through-the-Silicon Via Planning and Pin Assignment for Thermal and Wire Length Optimization in 3D ICs, Integration, the VLSI Journal. 2010

[2] Bei Yu(*), Sheqin Dong, et al, Voltage and Level-Shifter Assignment Driven Floorplanning,IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences,Vol. E92-A, No.12, Dec.2009

[3] Yaoguang Wei, Sheqin Dong, Xianlong Hong, APWL-Y:an accurate and efficient wirelength estimation technique for hexagon/triangle placement, Integration, the VLSI Journal, Integration, the VLSI Journal, 40 (2007), p406-419

[4] Chen S, Dong SQ, Hong XL, Yici Cai, Chung-Kuan Cheng, Jun Gu, “VLSI block placement with alignment constraints”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 53 (8): 622-626 AUG 2006

[5] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “An Integrated Floorplanning with an Efficient Buffer Planning Algorithm”, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 24 (No. 4) (2005)

[6] Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, C.K. Cheng, Jun Gu, “Non-slicing Floorplan and Placement using Corner Block List Topological Representation”, IEEE Transaction on CAS, Vol. 51 (No. 5) (2004), pp228-233

[7] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks”, ACM Transactions on Design Automation of Electronic Systems, Vol. 9 (No. 2) (2004), p199-211

[8] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “Floorplanning with Abutment Constraints Based on Corner Block List”, Integration, the VLSI Journal, Vol. 31 (No. 1) (2001), p65-77

[9] Sheqin Dong, Xianlong Hong, Song Chen, Xing Qi, Ruijie Wang, “VLSI Module Placement with Preplaced Modules and Considering Congestion Using Solution Space Smoothing”, IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E86-A, (No.12) (2003), pp3136-3147

[10] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation”, IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E84A (No. 11) (2001), p2697-2704

[11] Bei Yu, Sheqin Dong, et al, Floorplanning and Topology Generation for Application-Specific Network-on-Chip,ACM/IEEE ASP-DAC 2010,

[12] Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K.Cheng, Bus Via Reduction Based on Floorplan Revising, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010

[13] Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto, A Revisit to Voltage Partitioning Problem, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010

[14] Wentao Sui, Sheqin Dong, Jinian Bian, Wirelength-Driven Force-Directed 3D FPGA Placement,ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010

[15] Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto, Fixed Outline Multi-Bend Bus Driven Floorplanning,ACM/IEEE ISQED 2010, USA,

[16] Xu He, Sheqin Dong,Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning, ACM/IEEE ISQED 2009, USA, pp740-745

[17] Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K. Cheng, A Novel Fixed outline Floorplanner with Zero Deadspace for Hierarchical Design, ACM/IEEE International conference on CAD, 2008, USA,pp16-23

[18] Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang (Tsinghua Univ., China), Satoshi Goto (Waseda Univ., Japan), Symmetry Constraint based on Mismatch Analysis for Analog Layout in SOI Technology, The 13th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2008), Korean, January,2008

[19] Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong, “Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation” The 12th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2007), Yokohama, Japan, 2007.1

[20] Hongjie Bai, Sheqin Dong, Xianlong Hong, Congestion driven buffer planning for X-Architecture, ACM/IEEE ISQED 2007, USA,pp835-840

[21] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Fast Custom Instruction Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design”, IEICE Trans. Fundamentals, Vol. E91-A, No.6, pp. 1478-1487, June 2008.

[22] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Exploring Partitions based on Search Space Smoothing for Heterogeneous Multiprocessor System”, IEICE Trans. Fundamentals, Special Section on Nonlinear Theory and its Applications, Vol. E91-A, No.6, pp.2456-2464, Sep.2008.

[23] Hong Xianlong, Ma Yuchun, Dong Sheqin, Cai Yici, C.K. Cheng, Jun Gu, “A Floorplanning Representation Corner Block List and The Corner Block List Based Floorplanning Algorithm with Boundary Constraint”, SCIENCE IN CHINA (Series F), Vol. 47 (No. 1) (2004), p1-19

[24] Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, “A Buffer Planning Algorithm for Chip-Level Floorplanning”, SCIENCE IN CHINA SERIES F-INFORMATION SCIENCES 47 (6): 763-776 DEC 2004

[25] Yuchun Ma, Xianlong Hong, Sheqin Dong, C.K.Cheng, Jun Gu, “General Floorplans with L/T-shaped blocks using corner block list”, Journal of Computer Science and Technology vol.21, no. 6, Nov,2006 pp.922-926

[26] Dong Sheqin, Hong Xianlong, Wu Youliang, Gu Jun, “Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle”, Journal of Computer Science and Technology (JCST), Vol. 18 (No. 6) (2003), p739-746

[27] Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, C-K Cheng, Jun Gu, “Fast Evaluation of Bounded Slice-line Grid”, Journal of Computer Science and Technology (JCST), Vol. 19 (No. 6) (2004), p973-980

[28] Sheqin Dong, Shuo Zhou, Xianlong Hong, Chungkuan Cheng, Jun Gu, Yici Cai, “An Optimum Placement Search Algorithm Based on Extended Corner Block List”, Journal of Computer Science and Technology (JCST), Vol. 17 (No. 6) (2002), p699-707

[29] Di Long; Xianlong Hong; Sheqin Dong;“Signal-path driven partition and placement for analog circuit” Design Automation, 2006. Asia and South Pacific Conference on 24-27 Jan. 2006 Page(s):6

[30] Renshen WANG, Sheqin DONG Xianlong HONG, “An Improved P-admissible Floorplan Representation Based on Corner Block List”, 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1115-1118

[31] Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu, “LFF Algorithm for Heterogeneous FPGA Floorplanning”, 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1123-1126

[32] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, “An Integrated Floorplanning with an Efficient Buffer Planning Algorithm”, 2003.3, ACM/SIGDA International Symposium on Physical Design, USA

[33] Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, C-K Cheng, Jun Gu, “Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis”, 2003.6, IEEE/ACM 40th Design Automation Conference, Los Angeles, USA, p 806-811

[34] Shuo Zhou, Sheqin Dong, Xianlong Hong,Yici Cai, C-K Cheng, Jun Gu, “ECBL: An Extended Corner Block List with Solution Space including Optimum Placement”, 2001.3, ACM/SIGDA International Symposium on Physical Design, USA, pp150-155

[35] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, “Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List”, 2001.6, IEEE/ACM 38th Design Automation Conference, Las Vegas, USA, p770-775

[36] Xianlong Hong, Gamg Huang, Yici Cai, Sheqin Dong, Jiangchun Gu, C.K. Cheng, Jun Gu, “Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan”, 2000.11.5, IEEE/ACM International Conference on CAD, p8-12