计算机科学与技术系

Department of Computer Science and Technology

  • Hailong YAO
  • Assistant Professor
  • Department of Computer Science and Technology
  • Joined Department: 2009
  • Email:hailongyao@tsinghua.edu.cn
  • URL:http://learn.tsinghua.edu.cn:8080/2009990119/hailongyao.html
  • Phone:+86-10-62795403
  • Fax:+86-10-62781489

Education background

Bachelor of Computer Science, Tianjin University, Tianjin, China, 2002;

Ph.D. in Computer Science & Technology, Tsinghua University, Beijing, China, 2007.

Areas of Research Interests/ Research Projects

VLSI Physical Design, Design-Manufacturing Interface.

National "He Gao Ji" Major Project: Development of Advanced EDA Platforms (2008-2010).

Research Status

After graduation in 2007, I worked with Prof. Andrew B. Kahng as a postdoctoral scholar in Department of Computer Science and Engineering, UC San Diego. In my postdoctoral research, I focused on the areas of design for manufacturing, delay and leakage optimization, etc. Collaboratively, we published several papers, including one DAC 2008 paper and one ICCAD 2008 paper (Best Paper Nomination). We also filed a patent in UCSD. Besides, two journal papers have been accepted by IEEE Trans. on CAD of Integrated Circuits and Systems. My current research group focuses on the area of VLSI physical design, including topics of floor-planning, placement, routing, clock tree synthesis and routing, timing analysis and optimization, etc.

Honors And Awards

ICCAD 2006, 2008: Best Paper Nomination (2006, 2008);

CCF (China Computer Federation) Outstanding Ph.D. Thesis Nomination (2007);

Tsinghua University Outstanding Ph.D. Thesis Award, Second Class (2007).

Academic Achievement

[1] A. B. Kahng, C.-H. Park, X. Xu, and H. Yao (correspondent author). Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. on CAD of Integrated Circuits and Systems, Accepted.

[2] K. Jeong, A. B. Kahng, C.-H. Park, and H. Yao (correspondent author). Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. on CAD of Integrated Circuits and Systems, Accepted.

[3] H. Yao, S. Sinha, J. Xu, C. Chiang, Y. Cai, and X. Hong. Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits, Devices & Systems, vol. 2, no. 1, pp. 2-15, 2008.

[4] H. Yao, Y. Cai, Q. Zhou, and X. Hong. Multilevel routing with redundant via insertion. IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1148-1152, 2006.

[5] A. B. Kahng, C.-H. Park, X. Xu, and H. Yao (speaker). Layout Decomposition for Double Patterning Lithography. Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2008), 2008, pp. 465-472. (Best Paper nomination)

[6] K. Jeong, A. B. Kahng, C.-H. Park, and H. Yao (speaker). Dose Map and Placement Co-optimization for Timing Yield Enhancement and Leakage Power Reduction. Proc. IEEE/ACM Design Automation Conference (DAC 2008), 2008, pp. 516-521.

[7] H. Yao, S. Sinha, C. Chiang, X. Hong, and Y. Cai. Efficient Process-hotspot Detection Using Range Pattern Matching. Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2006), 2006, pp. 625-632. (Best Paper nomination)