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System-Level Performance Considerations Under the Peak Temperature Constraint

Jun 9, 2010 00:00

Title: System-Level Performance Considerations Under the PeakTemperature Constraint

Speaker:Xiaobo Sharon Hu, professor in the department of Computer

ScienceEngineering at the University of Notre Dame, Notre

Dame, Indiana, USA.

Time: June 10, 2010 10:00am-12:00am

Venue: East Main Building 8-402


As CMOS technology continues its downward scaling trends, increase in power density has promoted temperature-aware design to a prominent position in the design cycle. High chip temperature has severe impact on reliability, performance, cost, power consumption. Though chip packaging cooling solutions can be employed to hle worst-case temperature profiles, such solutions can be prohibitively expensive, since the cost of cooling solutions increases super-linearly in power consumption. A more economical way to limit chip temperature is to use processor throttling at run time: when the chip temperature exceeds some pre-specified threshold,the processor power consumption performance are temporarily reduced by hardware or the operating system. However, throttling can cause significant, difficult-to-predict, increase in response times. In general-purpose computing, throttling may lead to significant performance loss. In real-time systems, throttling may cause more deadline misses.This talk focuses on two key issues arising from the deployment of processor throttling: (1) finding a throttling schedule that maximizes the work completed under a given maximum temperature constraint, (ii) determining whether a set of real-time requirements can be satisfied for a specific throttling policy. Observations gained from working on these issues can be useful for solving other temperature-aware design problems.


Xiaobo Sharon Hu is a professor in the department of Computer Science Engineering at the University of Notre Dame, Notre Dame, Indiana, USA. She also holds a joint appointment in the department of Electrical Engineering at the same university.She received her Ph.D. degree from Purdue University. Her research interests include real-time embedded systems, low-power system design, VLSI nano-scaling computing. She has published more than 160 papers in these areas, received the Best Paper Award from the ACM/IEEE Design Automation Conference in 2001 from the IEEE Symposium on Nanoscale Architectures in 2009. Another paper of hers was named one of "The Most Influential Papers of 10 Years Design, Automation, Test in Europe Conference (DATE)".She received the CAREER award from U.S. National Science Foundation. She is currently Associate Editor for ACM Transactions on Embedded Computing. She also served as Associate Editor for IEEE Transactions on VLSI ACM Transactions on Design Automation of Electronic Systems, as guest editors for several different journals/magazines such as the IEEE Computer Magazine IEEE Transactions on Industrial Informatics. For more detailed information about Sharon Hu, please visit her webpage at www.nd.edu/~shu.