Education background
Graduation from Tsinghua University ( Automatic C ontrol) , Beijing, China, 1970.
Social service
China Computer Federation: Vice Chair of CAD and Graphics Professional Committee (2001-);
Journal on Computer Aided Design and Computer Graphics: Associate Editor-in-Chief (2004-);
IEEE International Conference on Field Programmable Technology (FPT 2010): General Chair (2010);
The 16th China National Conference on Computer Aided Design and Computer Graphics (CADCG 2010 ): General Chair (2010 ).
Areas of Research Interests/ Research Projects
Design Automation for Digital Systems in System, RTL and logic Levels
National Natural Science Foundation of China: Research on System Partitioning and Interface Synthesis of Multi-Target and Granularity Self-Adaptive SOC (2002-2005);
National Natural Science Foundation of China: Research on TLM F ormal V erification Techniques based on Next- G eneration V erification E ngines (2008-2011);
National Basic Research Program of China (The 973 Program): Efficient Design, V erification and T esting Techniques for P rocess C hips (2005-2010).
Research Status
My research interests include synthesis and verification techniques of all Logic, RTL and system levels.
In the 80s, my research group was dealing with technical study and CAD tool development. We have developed a simulation tool for logic and switch levels, which is part of PANDA-a VLSI CAD system used by industry world. This work has won National Award for Science and Technology P rogress.
In the 90s , we focused the research of combining l ogic synthesis with l ayout. We have proposed a re-synthesis approach after placement, and used re-wiring technique ( collaborated with Prof. David Yu-liang Wu's group at the Chinese University of Hong Kong) to improve the circuit structure and reduce the wire-length and delay time of critical paths.
After 2000, my research group has dealt with synthesis and verification techniques for RTL and system levels. We have built a platform for SOC synthesis, which consists of hardware/software partitioning, architecture synthesis, interface implementation, and behavior synthesis combined with floor-planning. As of RTL verification, we have proposed and implemented a novel hybrid SAT solver named EHSAT. This work was presented in Design Automation Conference 2007-a top conference in this area.
Now, we are focusing on the research of description verification with SystemC and TLM (Transaction Level Modeling). We used hybrid SAT and SMT solvers to solve the problems in generating the random stimuli based on constraints.
Honors And Awards
National Excellent Science & Technology Book Award and S&T Progress Award by National Press and Publication Administration, First Class-CAD Technique for VLSI(1999);
The 4th National Book Award by National Press and Publication Administration, Nominee-
CAD Technique for VLSI(1999);
Higher-Education Teaching Achievement Award by City of Beijing, Second Class (2001).
Academic Achievement
[1] Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong, Kang Zhao. Constrained Stimulus Generation with Self-adjusting Using Tabu Search with Memory.IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.Vol.E92-A, No.12, pp 3086-3093. 2009.
[2] Junbo Yu, Qiang Zhou, Gang Qu and Jinian Bian, Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation,IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A, (No.12), pp 3151-3159, 2009.
[3] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis.IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Vol.E92-A, No.9, pp 2283-2294, 2009
[4] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, "Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System".IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Val. E91-A, no. 9, pp 2456-2464, 2008.
[5] Tong, Kun, Bian, Jinian, Wang, Haili, "A cooperative universal data model platform for the data-centric electronic system-level design", Advanced Engineering informatics, val. 22, no. 3, pp 296-306, 2008.
[6] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, "Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design",IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, val. E91-A, no.6, pp 1478-1483, 2008.
[7] Ming Zhu,Jinian Bian, Weimin Wu: "A novel collaborative scheme of simulation and model checking for system properties verification",Computers in Industry,special issue: Collaborative Environments for Concurrent Engineering,Elesvier, val.57, no.8-9, pp 752-757, 2006
[8] Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao, "EHSAT: An RTL Satisfiability Solver Using an Extended DPLL Procedure",Proc. 44th Design Automation Conference(DAC'07), San Diego, California, USA, pp 588-593, 2007
[9] Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng, "A Novel Fixed-outline Floorplanner with Zero Deadspace for Hierarchical Design",Proc. The 2008 IEEE/ACM International Conference on Computer-Aided Design,(ICCAD'08), San Jose, CA, USA, pp 16 - 23, 2008.
[10] Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao, "Self-Adjusting Constrained Random Stimulus Generation Using Splitting Evenness Evaluation and XOR Constraints",Prof. 14th Asia and South Pacific Design Automation Conference, (ASPDAC'09), Yokohama, Japan, pp 769 - 774, 2009.
[11] Junbo Yu, Qiang Zhou, Jinian Bian, "Peak Temperature Control in Thermal-aware Behavioral Synthesis through Allocating the Number of Resources",proc. 14th Asia and South Pacific Design Automation Conference(ASPDAC'09), Yokohama, Japan, pp 85 - 90, 2009.
[12] Junbo Yu, Qiang Zhou, Gang Qu, and Jinian Bian, "Behavioral Level Dual-Vth Design for Reduced Leakage Power with Thermal Awareness", Proc. The 10th Design, Automation and Test, (DATE'10), Dresden, Germany, 2010. 3. 8-12, pp 1261-1266, 2010
[13] Dawei Liu, Qiang Zhou, Jinian Bian. Density smoothing method considering wire-length and overlap.Journal of Computer-Aided Design and Computer Graphics,v 22, n 4, pp 676-681+688, 2010. (In Chinese)
[14]YanniZhao,JinianBian,ShujunDeng. Constraints decomposition for RTL verification by SMT.Journal of Computer-Aided Design and Computer Graphics, v 22, n 2, pp 234-239, 2010. (In Chinese)
[15] Junbo Yu, Qiang Zhou, Jinian Bian. Thermal-aware resource usage allocation,Journal of Computer-Aided Design and Computer Graphics, v 21, n 9, pp 1257-1263, 2009 (In Chines)
[16] Kun Tong; ,Jinian Bian. Survey on transaction level modeling for system-on-chip design.Journal of Computer-Aided Design and Computer Graphics, v 19, n 11, pp 1365-1372, 2007 (In Chinese)
[17] Zhipeng Liu, Jinian Bian, Qiang Zhou. Overview of power optimization in high level synthesis.Journal of Computer-Aided Design and Computer Graphics, v 19, n 11, pp 1373-1380, 2007. (In Chinese)
[18] Kang Zhao, Jinian Bian, Sheqin Dong. Specific instruction-set automated customization based on clustering ILP model,Journal of Computer-Aided Design and Computer Graphics, v 19, n 10, pp 1229-1234, 2007 (In Chinese)
[19] Zhipeng Liu, Jinian Bian, Zhen Zhao, Qiang Zhou. ILP-based algorithm for peak power and max module power minimization in behavioral synthesis.Journal of Computer-Aided Design and Computer Graphics,v 19, n 8, pp 966-972, 2007 (In: Chinese)
[20] Shujun Deng, Weimin Wu, Jinian Bian.Hybrid satisfiability solving for RTL verification.Journal of Computer-Aided Design and Computer Graphics,v 19, n 3, pp 273-278+285, 2007 (In Chinese)
[21] Jinian Bian, Hongxi Xue, Ming Su, Weimin Wu.Design Automation for Digital Systems, 2nd edition (In Chinese). Tsinghua University Press, Beijing, 2005.
[22] Xianlong Hong, Weiping Liu, Jinian Bia, et al.CAD Technique for VLSI,(In Chinese). Defense Industry Press, Beijing, 1998.
